Design and Deployment of Deep Learning Applications on Edge Computing Platforms. ALOHA at SLOHA 2021

 



The SLOHA Workshop's primary goal is to address these research questions and facilitate the implementation of DL applications on heterogeneous low-power computing platforms and edge devices, including accelerators such as (embedded) GPUs, FPGAs, CGRAs, and TPUs. SLOHA 2021 (System-level Design Methods for Deep Learning on Heterogeneous Architectures) will be virtually held on February 5, 2021.

The ALOHA consortium will propose several presentations of the ALOHA framework during SLOHA 2021, which is co-located with Date Conference 2021 (Conference on Design, Automation and Test in Europe).

 

Overview and scope:

Machine learning, particularly deep learning (DL), is the most quickly growing domain of artificial intelligence. DL is being applied in more and more disciplines for recognition, identification, classification, and prediction tasks. A large part of the activities is focused on image, video and speech processing, but more general signal processing tasks also benefit from DL.

Prominent application areas and markets include human-machine interaction using vocal commands, biological signals processing on wearable devices for medical and fitness applications, visual environment understanding applications such as those used in robotics and advanced driver assistance systems, or predictive maintenance in industrial automation. These applications are often embedded into a broader technical context, imposing stringent constraints on power and size. Thus, many applications should be executed on highly customized heterogeneous low-power computing platforms at the edge.

While on the one hand, there exists a large zoo of DL models and tools that target standard hardware platforms, there are many challenges when targeting heterogeneous and edge devices on the other hand. Several software and hardware design choices have to be made when developing such systems. How to automate the search for and efficiently deploy or synthesize a neural network on multiple target platforms, such as different heterogeneous low-power computing platforms and edge devices? How should the neural network look like to achieve the best possible result on a given hardware platform with limited computing power and energy budget?

The workshop's primary goal is to address these research questions and facilitate the implementation of DL applications on heterogeneous low-power computing platforms and edge devices, including accelerators such as (embedded) GPUs, FPGAs, CGRAs, and TPUs.

Topics of the SLOHA Workshop include, but are not limited to:

  • System-level design methods (e.g., scheduling, mapping) for DL
  • Design space exploration and optimization (accuracy, performance, energy efficiency, robustness, security and other non-functional properties)
  • Modeling of hardware-agnostic neural networks
  • Deep compression, quantization and pruning techniques for edge devices
  • Heterogeneous computing platforms, edge devices, neuromorphic hardware for DL
  • Modeling of DL target platforms
  • Compilers, code generators, and synthesis tools for deployment
  • Signal processing applications, use cases, and best practices

The workshop will also present some of the methods, tools, architectures, and results achieved in the European Union's Horizon 2020 project ALOHA (https://www.aloha-h2020.eu) and the KISS project (https://www.iis.fraunhofer.de/kiss) funded by the German Federal Ministry of Education and Research.



Program:

15:00 – 15:10. Welcome and Introduction, Frank Hannig
15:10 – 15:50. Keynote Speech 1: In-Sensor ML — Heterogeneous Computing in a mW, Luca Benini
15:50 – 16:30. Session 1: Deep Learning at the Edge. Chair: Matthias Ziegler
15:50 – 16:00. Enabling Energy Efficient Machine Learning on a Ultra-Low-Power Vision Sensor for IoT,  Francesco Paissan, Massimo Gottardi, and Elisabetta Farella
16:00 – 16:10. Bit Error Tolerance Metrics for Binarized Neural Networks , Sebastian Buschjäger, Jian-Jia Chen, Kuan-Hsun Chen, Mario Günzel, Katharina Morik, Rodion Novkin, Lukas Pfahler, and Mikail Yayla
16:10 – 16:13. Fast Exploration of Weight Sharing Opportunities for CNN Compression, Etienne Dupuis, David Novo, Ian O'Connor, and Alberto Bosio
16:13 – 16:16. Pick the Right Edge Device: Towards Power and Performance Estimation of CUDA-based CNNs on GPGPUs, Christopher A. Metz, Mehran Goli, and Rolf Drechsler
16:16 – 16:19. QoS-Aware Power Minimization of Distributed Many-Core Servers using Transfer Q-Learning, Dainius Jenkus, Fei Xia, Rishad Shafik, and Alex Yakovlev
16:30 – 16:40. Break
16:40 – 17:30. Session 2: Autonomous Vehicles. Chair: Paolo Meloni
17:30 – 17:35. Short Break
17:35 – 18:15. Session 3: Deep Learning Applications on Programmable Hardware.  Chair: Matteo Spallanzani
17:35 – 17:45. Design and Deployment of Deep Learning Applications on Edge Computing Platforms: The ALOHA Framework, Paolo Meloni
17:48 – 17:51.Transparent FPGA Acceleration with TensorFlow, Simon Pfenning, Philipp Holzinger, and Marc Reichenbach
17:51 – 17:54. Hardware-efficient Residual Networks for FPGAs, Olivia Weng, Alireza Khodamoradi, and Ryan Kastner
17:54 – 18:04. Benchmarking Quantized Neural Networks on FPGAs with FINN, Quentin Ducasse, Pascal Cotret, Loïc Lagadec, and Robert Stewart
18:04 – 18:14. Why is FPGA-GPU Heterogeneity the Best Option for Embedded Deep Neural Networks?, Walther Carballo-Hernández, Maxime Pelcat, and François Berry
18:15 – 18:55. Keynote Speech 2: Specialization in Hardware Architectures for Deep Learning, Michaela Blott
19:00. Closing

Contacts

Project Coordinator
Giuseppe Desoli - STMicroelectronics
giuseppe(dot)desoli(at)st(dot)com

Scientific Coordinator
Paolo Meloni - University of Cagliari, EOLAB
paolo(dot)meloni(at)diee(dot)unica(dot)it

Dissemination Manager
Francesca Palumbo - University of Sassari, IDEA Lab
fpalumbo(at)uniss(dot)it

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